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پایان نامه مدل سازی سد شاتکی

Electrical Characterisation and Modelling of Schottky barrier

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The motivation for the work presented in this thesis originates in the semiconductor

industry’s drive to create increasingly scaled transistors. In view of current device dimensions

approaching fundamental atomic scales, the industry is looking to alternative

structures to provide continued scaling capabilities.

The use of metal, usually silicide, source and drain regions to create Schottky barrier

(SB-)MOSFETs is one such approach. Previous work on static and RF electrical characterisation

as well as simulations has shown this device to provide a number of scaling

benefits to the planar MOSFET structure. In addition, it provides simpler and more cost

effective fabrication.

In this work, the electrical properties under DC bias conditions of p-channel SBMOSFETs

with PtSi sources and drains are explored at room temperature and down to

80 K. High room temperature ON currents up to 545 mA/mm and transconductances

up to 640 mS/mm for 85 nm gate length devices are measured and performance factors

are found to satisfy ITRS recommendations. Increasing silicide anneal temperatures lead

to increases in Schottky barrier height and corresponding decreases in drain current are

observed.

The radio-frequency performance at frequencies up to 110 GHz is studied using a novel

measurement deembedding technique. High unity-gain cutoff frequencies up to 71 GHz

are extracted. Finally, two-dimensional simulations using the drift-diffusion simulator

MEDICI are performed and fitted to the measured electrical characteristics.


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کد امنیتی : ریست تصویر